1. Field of the Invention
The invention relates to integrated circuit type semiconductor memories organized in rows and columns and, more particularly, in such memories, it relates to a circuit to keep the column voltage constant during the recording.
2. Discussion of the Related Art
A standard type of semiconductor memory comprises, for example, about 16 million memory cells (16 megabits) that are organized in 32 sectors of 512,000 bits, each sector containing 64,000 words of eight bits each.
Broadly speaking, and as an indication, it may be said that an integrated, non-volatile, electrically erasable programmable memory 10 (FIG. 1) comprises memory cells, each including an N type floating-gate MOSFET transistor, Cl1 to CN1 for the first column BL1 (also called a bit line) and C1n to CNn for the last column BLn. The selection of a memory cell that is located at the intersection of a column and a row is done by a column-addressing circuit 11 and a row-addressing circuit 12. For each column, the indication of the binary value of the information element to be recorded in a memory cell is obtained by a programming circuit 13. The columns are connected to a voltage generator 14 that gives a voltage U.
The row-addressing circuit 12 receives the address code of a row and gives one of the row selection signals R1 to RN which is applied to the gate G of the transistors of the same row.
The column-addressing circuit 11 has two decoding circuits 11.sub.1 and 11.sub.2, each receiving a part of the address code of a column and each giving a signal for the selection of a column that is applied to the gate G of one of the transistors T21 to T2n or T31 to T3n which are N-type MOSFET transistors.
The circuit 13 for programming the binary value to be recorded in the memory cell comprises one P type MOSFET transistor (T11 to T1n) per column which receives the binary value 0 or 1 at its gate, by means of a matching circuit 131 to 13n.
In a column such as BL1, the transistors T11, T21, T31 are series-connected while the transistors C11 to CN1 are each in parallel between a column and a row, the drain being connected to the column and the sources of;all the transistors being connected to a supply circuit (not shown).
In the memory that has just been described briefly with reference to FIG. 1, the recording of the information elements in the memory cells is preceded by an operation to erase all the cells so as to place them in a determined state, for example the state 1 which corresponds to the absence of electrons in the floating gate of the transistor of the memory cell. For the recording of a word, only the cells that have to record a 0 state will be selected for the simultaneous application, to these cells, of an appropriate voltage to the drain (for example 5-7 volts) and to the gate (for example 12 volts) while the source remains at zero volts. The voltage U is diverted towards the bit lines by the column addressing circuit 11 and the programming circuit 13.
The different operations that are carried out in the memory are under the control of the signals given by a memory control circuit 9 which is of any known type.
In such an assembly, the drops in voltage, which are due to the parasitic resistance and transfer resistance of the transistors of the programming circuit 13 and addressing circuit 11, lower the voltage applied to the column BL which depends on the current in the column.